Flash memory is a non-volatile memory that can be electrically erased and reprogrammed. As flash memory is non-volatile, there is no need to have power to maintain the information stored in the chip. Also, flash memory, when packaged in a, e.g., “memory card,” is very durable. For these reasons, flash memory has gained popularity in the use of memory cards and USB flash drives for storage and transfer of data. Flash memory has also become the dominant technology wherever a significant amount of non-volatile, solid state storage is needed. For example, flash memory is used in many common devices such gaming consoles, digital cameras, laptop computers, digital audio players, and cellular telephones.
In traditional stacked flash memory, each memory cell includes two gates, e.g., a bottom floating gate and a top control gate. The floating gate is disposed above the MOSFET channel and is completely insulated about its periphery by an oxide layer. That is, an insulator layer is provided at the interface between the channel of the MOSFET and the floating gate, as well as between the interface of the floating gate and the control gate. The insulator layer (e.g., oxide) between the MOSFET channel and the floating gate is very thick, e.g., about 5-9 nm in thickness, in order to maintain a charge in the floating gate. See, e.g., FIG. 1 which shows a conventional stacked poly based flash memory.
However, the conventional stacked memory cell shown in FIG. 1 cannot be easily integrated into the manufacturing processes for microprocessors due to incompatibility with manufacturing processes of microprocessors. For example, the insulator layer between the floating gate and the MOSFET channel is thicker than required for conventional microprocessors, e.g., about 1 to 2 nm, in order to provide high performance transistors. Also, microprocessors do not include both a control gate and a floating gate, with an insulator layer therebetween.
As an alternative approach, a single poly NVRAM has been used to provide non-dense non-volatile memory functionality in standard CMOS processes. However, implementing the single poly NVRAM in SOI process presents unique challenges due to floating body effect. For example, the read margin is degraded due to dynamic lowering of the threshold voltage. Also, these non-dense devices are limited in application due to its density.
More specifically, as shown in FIG. 2, a single poly NVRAM includes a Si or BULK substrate that has a high voltage requirement, i.e., 7V bias, for the terminal in the program node. In BULK implementation, this high voltage can result in junction breakdown in the devices in the NVRAM and require complicated well-isolation techniques. This problem is mitigated in SOI implementation due to buried oxide (BOX) isolation. Also, as shown in FIG. 2, the coupling capacitor, NMOS read transistor and tunnel capacitor formed in the Si or BULK substrate, which need to be isolated by an STI structure. In BULK implementation, large capacitance between diffusion and wells significantly affects the performance of the cell. When migrated into SOI technology this parasitic capacitance is much smaller due to buried oxide. But in SOI transistors there is no direct contact to the well like in BULK transistors. This leads to floating body effects which reduces the threshold voltage of read transistor dynamically during the read operation and thus degrades the read margin of the cell.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.